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JOYSMT presents improvement of stability parameters of tantalum surface mounted capacitors with manganese dioxide or conductive polymer cathode. Higher stability is achieved by placement of the capacitor into an SMD case filled by an inert atmosphere and hermetically sealed. The long term stability testing performed on such hermetically sealed capacitors has proven better stability of both studied types – manganese dioxide capacitor and conductive polymer capacitor.
As companies start to implement lead free soldering processes, hand soldering and associated techniques have been identified as key functions in the manufacturing process requiring additional research and development.Hand soldering tends to occur at the end of the process line where the circuit board has a high intrinsic value and so correct process control will have a significant affect on manufacturing costs and productivity.
Embedded Passive Technology is a viable technology that has been reliably used in the defense and aerospace industry for over 20 years. Embedded Passive (Resistors and Capacitors) Technology have a great potential for high frequency and high density applications. It also provides better signal performance, reduced parasitic and cross talk. This paper summarizes the selection of resistor embedded materials, evaluations of resistive material and duplication of a complex digital design (Phase 2). –resistive materials (Foil 25Ω/sq NiCr and 1kΩ/sq CrSiO) and resistive-Ply materials (25Ω/sq and 250Ω/sq NiP) were chosen for evaluation.
End-product costs can rise consider- ably when engineering changes are made late in a printed circuit board’s (PCB’s) design and development cy- cle. Up to 80% of a new product’s cost is often committed by the first prototype build. This article provides practical and affordable Design-for- Test (DFT) and Design-for-Inspection (DFI) methods that will have a posi- tive impact on product costs, yield, reliability, and time-to-market. The properties of testability (including controllability and observability) will be analysed as they relate to analogue and digital design rules and their cause/effect, as well as the electrical and physical characteristics of proper PCB design.
Bottom-termination components (BTC), such as QFNs, are becoming more common in PCB assemblies. These components are characterized by hidden solder joints. How are defects on hidden DFN joints detected? Certainly, insufficient solder joints on BTCs cannot be detected by manual visual inspection. Nor can this type of defect be detected by automated optical inspection; the joint is hidden by the component body.
This document describes general guidelines and attention points for PCB design regarding selective soldering. The guidelines can be applied for Select Wave and/or Multi Wave soldering process in both leaded and lead- free alloy.When a PCB is designed according to these guidelines, a stable and solid solder-process can be guaranteed.
Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs, ADCs, and memory. They are susceptible to electrical, mechanical and thermal modes of failure like other components on a printed circuit board, but due to their materials, complexity and roles within a circuit, accurately predicting a failure rate has become difficult, if not impossible. Development of these critical components has conformed to Moore's Law, where the number of transistors on a die doubles approximately every two years. This trend has been successfully followed over the last four decades through reduction in transistor sizes creating faster,
The Semiconductor industry enabling today’s electronics market place is widely disseminated between multiple customer factions such as consumer electronics, telecommunications, automotive, medical devices, military, aerospace, industrial controls, embedded computing and other industries. A component’s life cycle for each industry varies drastically from 6 months to 10 years. The Semiconductor industry governed by realization of “Moore’s law” states doubling of the number of devices (or gates) per integrated circuit will occur, within a given geometric area
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