Influence of Pd Thickness on Micro Void Formation of Solder Joints in ENEPIG Surface Finish

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Influence of Pd Thickness on Micro Void Formation of Solder Joints in ENEPIG Surface Finish

Time: 2016-09-16 16:12:44 Source by: www.gladsmt.com

Influence of Pd Thickness on Micro Void Formation of Solder Joints in ENEPIG Surface Finish

We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less than 0.01mm line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd, Ni)Sn4 phase re- sulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd, Ni)Sn4 or creeping of (Pd, Ni)Sn4.

1.Introduction
There are many factors that affect the solder joint reliability in the commercial electronic packaging. Voids, especially, mi- cro-voids recently get more attention from industry because the line and space becomes finer and voids may have more po- tential to affect the solder joint reliability. Voiding in solder joint reliability heavily depends on the soleder materials and the surface finish.

In the case of solder materials, the use of lead in electronics is diminishing as the concerns on environmental issues are in- creasing. In particular, the European Union Waste Electrical and Electronic Equipment Directive (WEEE) and Restriction of Hazardous Substances Directive (RoHS) came into effect prohibiting the intentional addition of lead to most consumer elec- tronics produced in the EU in 2006. Lead-free solders may contain tin, copper, silver and traces of other metals such as bis- muth, indium, zinc and antimony. Tin-silver-copper alloys (Sn-Ag-Cu) are widely used in commercial electronic packaging.

Table 1 - Summary of test specimens.

Specimen	Ni,mm	Pd,mm	Au,mm
A	4.5±0.5	0.08±0.04	0.14±0.04
B	4.5±0.5	0.16±0.04	0.14±0.04
C	4.5±0.5	0.25±0.04	0.14±0.04
D	4.5±0.5	0.32±0.04	0.14±0.04

In the surface finish, new materials have also been adopted in electronic packaging. Electroless Nickel/ Immersion Gold (ENIG) has been commonly used as a surface finish. But it has a problem in solder joint reliability, which is caused by Ni corrosion during immersion gold deposition [1-6]. ENEPIG has been applied to printed circuit board (PCB) for electronic packaging to overcome the weak point of ENIG by adding Pd layer between Ni and Au. The Pd layer is known to prevent Ni from corrosion and to act as a barrier for Ni diffusion into solder during reflow, which results in continuous IMC layer. Another advantage of ENEPIG over ENIG is the cost reduction caused by substituting palladium for some of expen- sive gold.

Although Pd layer plays an important role in solder joint reliability, there have been a few of researches on the Pd layer, espe- cially on the optimum thickness for solder joint reliability. Among them, W.H. Wu reported that thick Pd layer had a detri- mental effect on the solder joint strength.

In the present study, we focused on the relation between micro-void formation and the Pd thickness among many factors for solder joint reliability. Micro-voids can have profound effect on the solder joint reliability in case that they reside around the IMC layer and form a continuous layer.

2.Experimental procedures
We prepared ENEPIG surface finish on ball grid array (BGA) circuit boards that have ball pads as depicted in Figure 1. The diameter of the pad was 300 m. The thicknesses of Ni and Au were 4.5±0.5 μm and 0.14±0.04 μm, respectively. We varied the thickness of the Pd layer from 0.08 to 0.32 μm as summarized in Table 1.

We attached LF35 type solder balls of 250 m in diamer on the ENEPIG pads. The test specimens were reflowed in reflow oven under nitrogen atmosphere with a peak temperature of 260 C.

We carried out the precon test (85 C/85% RH/3h + reflow 3 times) and the precon followed by TC test (-55 C ~125 C, 15 min) for every test specimen The test specimens were cold mounted using epoxy molding compound and cross-sectioned through a row of solder balls. They were mechanically polished with increasingly finer silicon carbide abrasive papers. The polished specimens were sometimes chemically etched using an etchant (10% hydrochloric acid + 90% methanol) to reveal the morphology of IMC.

We employed an optical microscope, a scanning electron microscope (SEM) with a field-emission gun and a focused ion beam (FIB) to analyze the micro-structure of the solder joint. We performed phase identification using energy dispersive X- ray spectroscopy (EDS) and SEM.

3.Results and Discussions
It shows the morphology of solder joint and the composition of IMC for specimen ‘B’ after a reflow. The ratio of the atomic percentage of (Cu+Ni) to Sn in the IMC is very close to 6:5, which suggests that the phase of IMC should be (Cu,Ni)6Sn5. Micro-voids were not frequently observed before reliability tests.

It compares the morphological changes after reliability tests for specimen ‘B’, ‘C’ and ‘D’. It shows that the number of micro-voids increases with the Pd thickness after precon and preceon+TC 200 cycles. The micro-voids lined up at the boundary between the Ni layer and solder. The micro-voids were mostly spherical and less than 0.01mm in diameter.

Cross-sectional FIB micrographs also indicates that there are micro-voids right above the (Cu, Ni)6Sn5 phase as shown. The micro-voids appear when the Pd thickness is greater than 0.00016 mm. The size of the micro-voids was less than 0.001 mm when the Pd thickness was 0.25 m. Another important change in the morphology as the Pd thickness increases is the occurrence of another phase above (Cu, Ni)6Sn5 layer.
EDS analysis identified the phase as (Pd, Ni)Sn4 as shown. We observed both micro-voids and (Pd, Ni)Sn4 when the Pd layer is thicker than 0.16 μm. (Pd, Ni)Sn4 phase is known to form during reflow and to be dispersed in the solder. The microstructure of (Pd, Ni)Sn4 is basically same as that of PdSn4, which is the phase formed in Pd-Sn diffusion couple.

A few of micro-voids existed even before the reliability test and the location of micro-voids was same before and after the reliability tests.Our results indicate that (Pd, Ni)Sn4 seems to be related to micro-void formation.

We can consider two possible mechanisms for micro-void formation with thick Pd layer. One is entrapping of volatile gas in the solder. Volatile gas mainly results from flux outgassing during reflow and usually escapes from the solder. But (Pd, Ni)Sn4 can block the movement of the gas as depicted. Similar voiding was observed in flash-gold finished component joints by W. Peng et al. They proposed that solid AuSn4 phase can increase the viscosity of the molten sol- der and restrict the egress of gasses from solder during reflow. P. Viswanadham also reported that the voiding increased with Au content in Sn-Pb solder joints. Similar voiding can be expected because the structure of PdSn4 is similar to that of AuSn4

Another explanation is the void formation by creep of (Pd, Ni)Sn4. The main deformation regime in Sn-based solder joints is known to be creep because of high homologous temperature (TH) defined by TH = TUse/Tm, where TUse is the temperature(K) at use and Tm is the melting temperature (K). When (Pd, Ni)Sn4 boarded by Sn grains moves by grain boundary

sliding, voids can form at the grain boundary as described. Such voids are usually filled by atomic diffusion through grain boundary. But micro-voids can form in the case of cyclic deformation such as TC. Both (Pd, Ni)Sn4 and Sn can be prone to creep because their melting temperatures are relatively low considering conventional operating conditions, which ranges from 25 C to 100 C. The homologous temperature for (Pd, Ni)Sn4 at room temperature is greater than 0.5Tm because the melting temperature (Tm) is 295 ]. S.W. Shin reported that void nucleation and growth were caused by creep in the lead-free solders. V.I. Igoshev mentioned that the grain boundary sliding can cause extreme heteroge- neity of plastic deformation and lead to reduction in the polycrystal compatibility by formation of voids at grain boundaries in lead-free solders.

Conclusions

We investigated the effect of the Pd layer thickness in ENEPIG on the micro-void formation of the lead-free solder joint, which could be one of crucial factors for solder joint reliability. We found that (Pd, Ni)Sn4 phase and micro-voids devel- oped simultaneously as the Pd layer thickened.

This study suggests that micro-void formation is closely related to the (Pd, Ni)Sn4 phase. We conclude that the Pd layer thickness should be well controlled to avoid micro-void formation. In our particular case, the maximum thickness allowable is 0.16 μm.

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