Counterfeit-Integrated-Circuits

The counterfeiting of electronic components has become a major challenge in the 21st century. The elec- tronic component supply chain has been greatly affected by widespread counterfeit incidents. A specialized service of testing, detection, and avoidance must be created to tackle the worldwide outbreak of counterfeit integrated circuits (ICs). So far, there are standards and  programs in  place for outlining the testing, documenting, and reporting proce- dures. However, there is not yet enough research addressing the detection and avoidance of such counterfeit parts. In this paper we will present, in detail, all types of counterfeits, the defects present in them, and their detection methods. We will then describe the challenges to implementing these test methods and to their effectiveness. We will present sev- eral anti-counterfeit measures to prevent this widespread counterfeiting, and we also consider the effectiveness and limitations of these anti-counterfeiting techniques.


Counterfeit ICs: The Problem
ounterfeiting and piracy are longstanding problems grow- ing in scope and magnitude. They are of great concern to government and industry because of  the negative impact they can have on innovation, economic growth, and employ- ment, the threat they pose to the welfare of consumers,
the substantial resources that they channel into crimi- nal networks, organized crime, and other groups that disrupt and corrupt society, and finally,  the loss of business from the trade in counterfeits . Based on a 2017 report by the International Chamber of Commerce, it was esti- mated that the cost of counterfeiting and piracy for G20 nations was as much as US$3775 billion every year and will grow to $5.7 trillion in 2017 .

Innovation in the business sector has always been the main driver of economic growth, through the development and implementation of ideas for new products and pro- cesses. These inventions are usually protected via patents, copyrights, and trademarks. However, without adequate protection of these intellectual property (IP) rights, the incentives to develop these new ideas and products would be considerably reduced, thereby weakening critical thinking and the innovation process . These risks are particularly high for those industries in which the research and devel- opment (R&D) costs associated with the development of new products are very high compared to the cost of pro- ducing the resulting products. In the world of electronics, the R&D costs for the semiconductor industry are indeed extremely high, and protection of their IP rights is of the utmost importance.Counterfeiting of integrated circuits has become a major
challenge due to deficiencies in the existing test solutions and lack of effective avoidance mechanisms in place. Over the past couple of years, numerous reports have pointed to the counterfeiting issues in the US electronics compo- nent supply chain. A Senate Armed Services public hearing on this issue and its later report clearly identified this as a major issue to address because of its significant impact on reliability and security of electronic systems.

As the complexity of the electronic systems, along with the ICs used in them, has increased significantly over the past few decades, they are assembled (fabricated) globally to reduce the production cost. For example, large foundries located in different countries can offer lower prices to the design houses. This globalization leads to an illicit mar-  ket willing to undercut the competition with counterfeit parts. If these parts end up in critical applications like defense, aerospace, or medical systems, the results could be catastrophic.

Just how big the market is remains a mystery. A study conducted from 2008–20014 reveals that 55% of original component manufacturers (OCM) and 58 % of distributors (authorized and unauthorized) have encountered counterfeit parts [70]. The Electronic Resellers Association Interna- tional monitors, investigates, and reports issues that are affecting the global supply chain of electronics. ERAI, in combination with Information Handling Services Inc.

With counterfeit incidents on the rise, it is increasingly important to analyze the vulnerabilities of the electronic component supply chain.  

There are a handful of standards that seek to do just this, with more being written and revised. The group respon- sible for many of these standards is the G-19 Counterfeit Electronic Parts Committee, set forth by SAE International [59]. Their standards target three different sectors of the industry: distributors, users, and test service providers (i.e., test laboratories). A collection of the standards that they have written or are currently working on is as follows: (i) AS6081 - Counterfeit Electronic Parts Avoidance, Dis- tributors, (ii) ARP 6178 - Counterfeit Electronic Parts; Tool for Risk Assessment of Distributors, Distributors & Users, (iii) AS5553 - Counterfeit Electronic Parts; Avoid- ance, Detection, Mitigation, and Disposition, Users, and (iv) AS6171 - Test Methods Standard; Counterfeit Elec- tronic Parts, Test Providers.

While SAE is the most prominent entity when it comes to standards, there are a couple of programs designed to help independent distributors gain customers'trust. Components Technology Institute, Inc. has created the Coun- terfeit Components Avoidance Program (CCAP-101). Independent distributors can be certified as CCAP-101 com- pliant, done by means of a yearly audit. Another program with similar goals has been developed by the  Indepen- dent Distributors of Electronics Association (IDEA) ]. A comparison of the SAE’s AS5553, CTI’s CCAP-101,  and IDEA’s STD-1010 is available. The main issue with many of these standards is that the “policy” and the“regulations” are their main focus rather than the “technol- ogy”. Thus it is easy for counterfeiters to adapt to the new regulations circumventing effective detection of counterfeit parts.
Detection and avoidance of counterfeit components are difficult challenges, partly because there are such a wide variety of counterfeit types impacting the supply chain. It is of the utmost importance to develop a taxonomy of defects and anomalies present in counterfeit components, to enable detection of these components with a group of test methods. In this paper, we have developed a comprehensive taxon- omy of counterfeit types, defects and test methods. 

(iii)Taxonomy of counterfeit detection methods: Our counterfeit methods taxonomy describes all the test methods currently available for counterfeit detection. Test methods for counterfeit detection primarily tar- get all the counterfeit parts already on the market (known as obsolete and active parts).
(iv)Taxonomy of counterfeit avoidance methods: The taxonomy of avoidance methods addresses how to prevent counterfeit parts from entering into supply chain and to identify counterfeit parts without per- forming the costly and time consuming detection methods.
(v)The rest of the paper isTaxonomy of counterfeit defects: We develop a detailed taxonomy of the defects present in coun- terfeit ICs. To the best of  our knowledge, this  is  the first approach to analyzing counterfeit compo- nents based on their defects and anomalies. This list of defects and anomalies is based on our detailed analysis of numerous counterfeit parts in collabo- ration with SAE G-19A, Test Laboratory Standards Development Subcommittee.

(vi)counterfeit methods taxonomy describes all the test methods currently available for counterfeit detection. Test methods for counterfeit detection primarily tar- get all the counterfeit parts already on the market (known as obsolete and active parts).
(vii)Taxonomy of counterfeit avoidance methods: The taxonomy of avoidance methods addresses how to prevent counterfeit parts from entering into supply chain and to identify counterfeit parts without per- forming the costly and time consuming detection methods.

tested, and shipped to the market. Any untrusted foundry/assembly that has access to a designer’s IP, also has the ability to fabricate ICs outside of contract. They can easily sell excess ICs on the open market.
4)Out-of-Spec/Defective: The other variation of an untrusted foundry/assembly sourcing counterfeit com- ponents is out of specification or rejected components. They may either knowingly sell these components, or the components may be stolen and sold on open mar- kets. During manufacturing tests, a component is con- sidered defective if it produces an incorrect response to even one test vector. Sometimes, the probability of activating a component’s defective node is extremely small. If these components make their way into the supply chain, detection will be extremely difficult as they produce correct responses in most of the test cases. These components can pose a serious threat to the quality and reliability of a system.
5)Cloned: Cloning is commonly used by a wide vari- ety of adversaries/counterfeiters (from small entity to large corporation) to copy a design in order to reduce the large development cost of a component. A cloned component is an unauthorized production without a legal IP. Cloning can be done in two ways – by reverse engineering, and by obtaining IPs illegally. In reverse engineering, counterfeiters copy designs and then man- ufacture (fabricate) components which are the exact copy of their original counterpart. Sometimes cloning can be done by copying the – contents of a memory used in a tag for electronic chip ID, bitstream targeted to programmable gate arrays, etc.
6)Forged Documentation: Forged documentation may include certifications of compliance for some stan- dards or programs, or a revision history or change-logtested, and shipped to the market. Any untrusted foundry/assembly that has access to a designer’s IP, also has the ability to fabricate ICs outside of contract. They can easily sell excess ICs on the open market.
4)Out-of-Spec/Defective: The other variation of an untrusted foundry/assembly sourcing counterfeit com- ponents is out of specification or rejected components. They may either knowingly sell these components, or the components may be stolen and sold on open mar- kets. During manufacturing tests, a component is con- sidered defective if it produces an incorrect response to even one test vector. Sometimes, the probability of activating a component’s defective node is extremely small. If these components make their way into the supply chain, detection will be extremely difficult as they produce correct responses in most of the test cases. These components can pose a serious threat to the quality and reliability of a system.
5)Cloned: Cloning is commonly used by a wide vari- ety of adversaries/counterfeiters (from small entity to large corporation) to copy a design in order to reduce the large development cost of a component. A cloned component is an unauthorized production without a legal IP. Cloning can be done in two ways – by reverse engineering, and by obtaining IPs illegally. In reverse engineering, counterfeiters copy designs and then man- ufacture (fabricate) components which are the exact copy of their original counterpart. Sometimes cloning can be done by copying the – contents of a memory used in a tag for electronic chip ID, bitstream targeted to programmable gate arrays, etc.

an electronic component will go through a process . This process includes design,  fabrica- tion, assembly, distribution, usage in the system, and finally end of life. As seen, there are vulnerabilities associated with each step in this supply chain. In design stage, an IP may be stolen or a hardware Trojan may be inserted into the design. An untrusted foundry or assembly can insert a hardware Trojan or produce different types of counterfeits. The design house can use illegally obtained IPs in their designs. Overproduced and out-of-spec/defective parts can be entered into the supply chain in the fabrication stage. Untrusted foundries can potentially sell these parts in the open market. They can also tamper with the design to cre- ate a backdoor for getting secret information from the field.These parts also get into the supply chain in the assembly phase. An untrusted assembly can possibly sell these parts or tamper the designs. Illegal activities during distribution, in-the-system (lifetime), and end-of-life may bring different types of counterfeits back into the supply chain (recycled, remarked, etc.).

Counterfeit Defects
The detection of counterfeit components is a multifaceted problem. Different types of components (analog, digital, etc.) and counterfeits  impact the detection results. Some counterfeits are easier to detect than others and some components are easier to test than others. To address this, it is of the utmost importance to develop a taxonomy of defects and anomalies present in the counterfeit components. By ensuring the detection of one or more defects, one can confidently detect counter- feit components. A counterfeit part may present anomalies on the leads/package,  degradation in  its  performance, or a change in specification. Since we assume, the compo- nents are comprehensively tested by the assembly, any such anomalies and defective behavior by them can be attributed to being counterfeit. Figure 4 presents the classification of the defects present in the counterfeit components.
Physical Defects
Physical defects are directly related to the physical proper- ties of the components. They can be classified as exterior and interior defects, depending on the location of the defects related to the packaging.
Exterior defects are related to packaging/shipping, leads/balls/columns, and package of a component. The most obvious defects will be ones  that  are  associated  with the packaging or shipping the parts arrived in. The leads/balls/columns of an IC can show how the part has been handled if it was previously used. Physically, they should adhere to datasheet specifications, including size and shape. The final coating on the leads should conform to the specification sheet. The package of an IC can reveal sig- nificant information about the chip. As this is the location where all model numbers, country of origin, date codes, and other information are etched, counterfeiters will try to be especially careful not to damage anything and to keep the package looking as authentic as possible.
Interior defects are mainly divided into two types: bond wire and die-related defects. Some common defects related to bond wires are missing/broken bond wires inside the package, a poor connection between the die and bond  wire, etc. The die reveals a significant amount of relevant information regarding the component. Die-related defects include die markings, cracks, etc.

Electrical Defects
Typical electrical defects can be classified into two distinct categories, namely parametric defects and manufacturing defects. Parametric defects are shifts in component param- eters due to prior usage or temperature. A shift in circuit parameters due to aging will occur when a chip is used in the field for some time. Manufacturing defects come from the fabrication process of components and are classified into three categories – process, material, and package. The defects under the process category come from the photo- lithography and etching processes during the fabrication. The defects related to material arise from impurities within the silicon or oxide layers. The passivation layer provides some form of protection for the die, but failure occurs when corrosion causes cracks or pin holes. The aluminum layer can easily be contaminated with the presence of sodium and chloride and results in an resistive open defect.


Counterfeit Detection Methods
It has become necessary for manufacturers, distributors, and users of electronic components to inspect all incom- ing electronic components for authenticity, especially with parts purchased outside of OCM-authorized distributors. It is absolutely necessary to analyze the current counterfeit detection methods for the inspection of such parts. In this section, we will describe these detection methods in detail. Figure 5 shows the detailed taxonomy of such methods.

Physical Inspections

Physical inspections are performed to examine the phys- ical and chemical/material properties of the component’s package, leads and die of a component mostly to detect the physical counterfeit defects.

1)Incoming Inspection: When an order is received, it first goes through the incoming inspection. All the components under test (CUTs) are inspected thor- oughly. In low power visual inspection (LPVI), all the CUTs are strictly documented and inspected. LPVI requires a low power microscope (generally less than 10X magnification) to inspect the exterior of the CUT. The markings on genuine components tend to be clear and identical. The internal structure of the CUTs are analyzed using X-Ray imaging. If a known good com- ponent (golden model) is available, one can compare the images taken from the CUT with this golden model.

2)Exterior Test: The exterior part of the package and leads of the CUT are being analyzed by using exterior tests. In package configuration and dimension analy- sis, the physical dimensions of the CUTs are measured either by hand-held or automated test equipment. Any abnormal deviation of measurement from the specifi- cation sheet indicates that the CUT may be counterfeit. Blacktop testing is the procedure of testing the marking permanency of a CUT with various solvents. A non- epoxy blacktop coating should be dissolved in acetone, while a thermal or UV-cured epoxy will require the use of a much more aggressive solvent [45]. Microb- lasting analysis is a dry and superfine blasting process. Various blasting agents with proper grain sizes are bombarded on the surface (package) of the CUT, and the materials are collected for analysis. Some com- mon blasting agents are aluminum oxide powder, glass beads, sodium bicarbonate powder, etc. Hermiticity testing is a special type of package analysis specific to hermetically sealed parts that tests the hermetic seal. The seal on such components ensures its correct oper- ation in the environment that it was designed for. A break in this seal leads to the failure of the component. Scanning acoustic microscopy (SAM) is one of the most efficient, though expensive, ways of studying the structure of a component. This technology functions by using the reflection or the transmission of ultrasound waves to generate an image of the component based on its acoustic impedance at various depths. This is very useful in detecting delamination [37]. Cracks and voids in the die will also be detectable, as well as the structure of bond wires.

3)Interior Test:  The  internal  structures,  die  and  bond wires, of the CUTs are inspected by delid/decapsulation. There are three mainstream meth- ods commercially available for decapsulation. These are chemical, mechanical, or laser-based products. Chemical decapsulation involves etching away the package with an acid solution. Newer laser-based tech- niques can remove an area of the package. Mechanical decapsulation involves grinding the part until the die is exposed. Once the part has been decapsulated and the required structures exposed, the following tests need to be performed:
In optical inspection, all the related information regarding die and bond wires are properly documented.

The relevant information regarding die markings (com- pany logo, date code, chip ID, country of manufacturer, etc.), bond wire positions, bond types, etc. are to be documented. The integrity of the bonds with the  die is tested using wire pull. The adhesiveness between die and bond wires degrades with time if the compo- nent is in the field. Comparison of the tension (pulling force) with the golden and test components determines whether it was used before or not. In die shear, die attach integrity is verified. This test is applicable to hermitic devices only. A ball shear test is applied to verify the ball bond integrity at the die. In scanning electron microscopy (SEM), the images of die, pack- age, or leads are taken by scanning it with a focused beam of electrons. If there is an anomaly present in it, it can easily be detected by SEM. It has an effective reso- lution up to a few nanometers which refers that the die can be analyzed down to its gate level. This is useful for a thorough analysis of the die.

4)Material Analysis: The chemical composition of the CUT is verified using material analysis. This is the only category of tests that can detect defects and anomalies related to materials. Defects such as wrong materials, contamination, oxidation of leads and pack- ages, etc., can be detected. There are several tests that can perform material analysis. Some of the most pop- ular tests are X-Ray fluorescence (XRF), fourier trans- form infrared spectroscopy(FTIR), ion chromatogra- phy (IO), Raman spectroscopy, and energy-dispersive X-ray spectroscopy (EDS).

4.2 Electrical Inspections

In this section, we will discuss various manufacturing tests suitable for detecting the defects and anomalies discussed in Section 3.2. An automatic test equipment  may be required for some of these tests

1)Parametric Tests: Parametric tests are performed to measure the parameters of a chip. If the chip has been used before, the DC and  AC  parameters may shift from their specified value (mentioned on the datasheet). After observing test results from a paramet- ric test, a decision can be made as to whether or not   a component is counterfeit. In DC parametric tests, the parametric measurement unit (PMU) of an ATE forces an I/O voltage and current to a steady state and measures the electrical parameters using Ohm’s law. The operating conditions are set carefully during mea- surement. The DC parametric tests can be classified  in different categories - contact test, power consump- tion test, output short current test, output drive current test, threshold test, etc. Detailed descriptions of each test can be found in [6]. In AC parametric tests, the measurement of AC parameters (terminal impedance, timing, etc.) is performed by using AC voltages with  a set of frequencies. AC parametric tests can be clas- sified as follows: rise and fall time tests, set-up, hold and release time tests, propagation delay tests, etc. A different set of parametric tests can also be applied to memories, DC parametric tests include volt- age bump test, leakage tests, etc. AC parametric tests include set-up time sensitivity test, access time test, running time test, etc.

2)Functional Tests: Functional tests are the most effi- cient way of verifying the functionality of a compo- nent. A majority of the defects from the defect taxon- omy can be detected by these tests. Any defects that impacts the functionality (from some easy defects such as missing or broken bond wires, missing or wrong dies, etc., to hard to detect defects related to pro- cess, material, and package) can be detected. In func- tion verification, the functionality of a component is verified. It determines whether individual components, possibly designed with different technologies, func- tion as a system and produce the expected response. In memory tests, read/write operations are performed on a memory to verify its functionality. MARCH tests [6, 48, 67] can be applied for counterfeit detection. Since the functions of memories are simple, exhaustive func- tional testing is possible and is normally used during manufacturing testing.

3)Burn-In Test: The reliability of a device is mainly ensured by burn-in [36]. In burn-in, the device is oper- ated at an elevated temperature to simulate a stress condition in order to find infant mortality failures and unexpected failures, to assure reliability. Burn-in test methods are described in MIL-STD-883 for integrated circuits and MIL-STD-750 for other discrete compo- nents [16, 17]. The implementation of burn-in is very important as it can easily weed out the commercial grade components marked as military grade. It can also remove defective components or those compo- nents that were not designed to perform under these stress conditions.

4)Structural Tests: Over the past decade, there has been a major shift toward using structural tests [18, 20, 55, 62] to reduce the overall cost of manufacturing tests. Structural tests are very effective in detecting manu- facturing defects (discussed in Section 3.2) for out-of- spec/defective counterfeit types. They can detect the cloned (reversed engineered) counterfeit components if there are some anomalies in the reverse engineering process. If the cloned netlist does not match with the genuine netlist for even few gates, some of the struc- tural test vectors will produce an incorrect response and the CUT will be flagged as  defective.  It  can  also detect some of the delay defects due to aging in while implementing anti-counterfeit measures. New mech- anisms can be put in place during the design of new chips that could help to prevent counterfeiting. As obsolete parts are no longer being manufactured, and active parts are being fabricated based on previous designs and developed masks, the focus should be on the detection of such counterfeit components and the implementation of avoidance measures at the package level. As we described earlier, at this point, all the standards are in place simply for detection. In this section, we will briefly discuss various anti-counterfeit mea- sures that can be implemented for new, active, and obsolete parts.shows the taxonomy of such anti-counterfeit measures.

5.2Package ID

The anti-counterfeit avoidance measures discussed so far only target new ICs. However, a large portion of the sup- ply chain is populated by active and obsolete components. There is no opportunity for adding any extra hardware to create a chip ID in those designs. For tagging such active and obsolete components, we need to create package IDs that do not require access to designs. No package mod- ifications are allowed during the generation of package IDs. These IDs can be used for new components as well. DNA markings, nanorods, and magnetic PUFs are the viable options for creating package IDs.

1)DNA Markings: Plant DNA  is  scrambled  to  cre- ate new and unique genetic sequences, and these sequences of DNA are integrated with inks. These inks are then applied on the packages of the IC at the end of the packaging process. Once the ICs are received, then, authentication includes first checking whether the ink fluoresces under specific light, and second, sending a sample of the ink to a lab to verify that the DNA  is   in the database of valid sequences [49]. Recently, the DOD mandated [72] that DNA marking be placed on the components in order to track them throughout the supply chain. DNA markings have several limitations that introduce some serious concerns of their applica- bility in counterfeit avoidance. The fast authentication achieved by observing the fluorescence of the marking under specific light can be imitated by counterfeit- ers, either with invalid DNA or other materials. But detailed DNA validation is extremely time-consuming and costly.

2)Nanorods: In this technique, a microscopic pattern
is created by growing an array of nanospheres into nanorods that are less than 100nm long [41]. Each time the process is repeated, the same pattern is created, but the exact angle and length of each individual nano-rod  varies, so that each set of nanorods is distinct. After the array of nanorods is grown, it is applied to a chip using a specialized printer. The chip can be authenticated by comparing the overall pattern and visual properties of each nano-rod to a database.
3)Magnetic PUFs: A magnetic PUF uses the inherent characteristics of magnetic stripes for unique identi- fication [30, 50]. Each magnetic stripe, due to the randomness of the creation process, has a noise-like component along with the data that is stored. This noise is unpredictable and difficult to clone, yet is consistent and repeatable, therefore acting as a PUF.


Detection and Avoidance Challenges
We  believe that research in  the detection and avoidance  of counterfeit electronic components is still in its infancy. There are major challenges that must be overcome in the development of effective test methods. In this section, we will discuss the counterfeit detection and avoidance chal- lenges that must be overcome in the near future.

2)Electrical Inspections: Electrical tests have the poten- tial to be an efficient means of counterfeit detection, as they do not have the limitations of physical inspections. However, there are major challenges that are unique  to electrical tests. In this section, we will briefly dis- cuss the limitations of the electrical tests described in Section 4.2.

Parametric tests are generally very time efficient. However, due to increased process variations and envi- ronmental variations (temperature, noise, aging, etc.), the electrical parameters of a component vary signifi- cantly. It will be very difficult to conclude whether the variations in the parameters of a component are due to the aging (for recycled and remarked components) or to the process variations in the circuit. One can per- form a statistical analysis based on the data observed from the parametric tests to determine the confidence level that a part is counterfeit with or without a golden IC. The efficiency of such analysis must be proven on a large number of golden and counterfeit parts.

For functional tests, test program generation for obsolete and active parts with limited knowledge of the part will be extremely difficult, if not impossi-  ble. The requirement of having a high-speed tester in order to apply functional test patterns to chips make it extremely expensive. It is nearly impossible to get the complete set of test vectors for an obsolete part from the OCM. In some cases, the OCM may no longer exist or the information required may no longer be avail- able in archived records at the OCM. Burn-in tests are useful in detecting infant mortality failures of com- ponents. However, because of excessive test time and cost, these tests are only attractive and useful only for critical and high-risk applications. The implementation of structural tests in counterfeit detection is extremely challenging for several reasons. First, the structural tests require total access to the internal scan chains of a component. Sometimes, IP owners do not give permis- sion to access their design and disable the internal scan chains with a fuse. Second, obsolete parts may not have design for testability (DFT) structures implemented. Finally, analog chips cannot be tested.


Avoidance Challenges

The techniques described in Section 5 pose several concerns for counterfeit avoidance. Table 2 presents the comparison study of all the different counterfeit avoidance technolo- gies. We have assigned a score of high, medium, or low, depending on effectiveness.

1)Reliability: This is a major issue that must be over- come for many of these techniques. For example, the response of a PUF must be constant for a given chal- lenge over a wide range of environmental variations, ambient noise, and aging. Active hardware metering does not have a reliability problem. However, its effec- tiveness for counterfeit avoidance is yet to be verified. There is a serious reliability concern on DNA marking as environmental conditions such as high temperatures can potentially damage the DNA and either make the sequence unreadable or change the sequence. The reli- ability of nanorods and magnetic PUFs have not yet been verified.

2)Uniqueness: This is a measure of uncorrelatedness

between two chip IDs. Ideally, two IDs should differ with a probability of 0.5 under the same test conditions. Better uniqueness makes it difficult for counterfeiters to guess new IDs after obtaining a set of IDs. PUFs and magnetic PUFs produce responses nearly equal to the ideal case [31, 44, 77]. Any high-level language (C/C++, Java, Matlab etc.) can generate a true ran- dom number, which is generally used as the chip ID. Due to the huge number of base pairs in DNA, there are enough sequences to support billions of unique markings. However, fast authentication – observing the specific light – can be easily imitated. The uniqueness of the marking is based on the number of nanorods in the pattern and the sensitivity of the measuring device to color and intensity of light. Since the exact angle of each individual nano-rod is random, it is very unlikely that the same process will produce the same result, and manually cloning the marking at a nano scale is not practical.

3)Tamper resistance: This is defined as the difficul- ties faced by the attacker/counterfeiter when attempt- ing to disable  the  counterfeit  avoidance  system.  It is extremely difficult to clone the IDs generated by PUFs and magnetic PUFs. The CDIR sensors also pro- vide high tamper resistance because they use natural random process variation. As the poly fuse provides excellent resistance against tampering, it is hard to alter the contents in poly fuse-based sensors. It is easy to clone the ECID, as it static  and readable. It is sim-  ple for counterfeiters to imitate the color generated by DNA markings, during fast authentication. The tamper resistance of nanorods has not yet been verified.

4)Area overhead: This is the area required on the  die to implement a counterfeit avoidance measure. PUFs, CDIR sensors and ECID provide low area overhead whereas hardware metering, SST, and poly fuse-based sensors offer medium area overhead. DNA markings, nanorods, and magnetic PUFs do not require any area overhead.

5)Target counterfeit types: This represents the detectable counterfeit types (from the counterfeit tax- onomy discussed in Section 2.1). PUFs and magnetic PUFs can detect remarked and cloned counterfeit types. SST can likely detect overproduced, out-of- spec/defective, and cloned component types. CDIR and poly fuse-based sensors are designed to target recycled and remarked types. ECID can potentially detect remarked type. DNA markings and nanorods may possibly be used to detect recycled and remarked counterfeit types.

6)Target components: This describes what type of com- ponents should be targeted for anti-counterfeiting. DNA markings, nanorods, and magnetic PUFs may be implemented in both analog and digital components, whereas the other anti-counterfeit measures can only target digital components.

7)Implementation  cost:   The  cost   of  implementing a PUF would entail storing and maintaining the challenge-response pairs in a secure database, in addi- tion to its area overhead.  For  hardware  metering  and SST, back-and-forth communication between the design house and foundry make it expensive to imple- ment. For CDIR and poly fuse-based structures, the cost comes from the area overhead. To authenticate the ICs, low-cost equipment is required. We need only a secure database to store the ECID. Thus, the cost from area overhead is negligible. The detailed authentica- tion for identifying the plant DNA applied to the IC is expensive.

We must make every attempt to stay ahead of counterfeit- ers to prevent the widespread infiltration of counterfeit parts into our critical infrastructures. This should begin with a necessary comprehensive assessment of current detection technologies. A particular set of methods may be useful when applied to a specific type of components such as microprocessors, memories, etc., but the same set of meth- ods may not extend to others such as analog ICs, transistors, etc.  Physical methods, on the other hand, can be applied  to all component types. However, some of  the  methods are destructive and take hours to implement. As a result, sampling is performed to certify a batch of parts by observ- ing a small number of parts. Electrical methods, on the other hand, are non-destructive and time efficient, but very difficult to implement.
We need to develop a test selection technique [27] that will consider test time, test cost, and application risks while recommending a set of tests to detect the defects and anoma- lies present in counterfeit components with high confidence. While selecting a set of tests from the complete test set, one should first be chosen that detects all high frequency defects (those that occur most frequently in the counterfeit compo- nents), to reach a quicker decision as to a component being counterfeit. This technique should allow us to perform the following:
1)Risk-Based Analysis: The model should consider application risks while recommending a set of tests. The test set should be different for different risks. For critical applications we need to concentrate on obtain- ing the maximum test coverage of counterfeit defects irrespective of test time and cost. We should also focus on test time and cost while developing the test set for other application risks.
2)Data-Driven Analysis: The model should be devel- oped on the data received from Government-Industry Data Exchange Program, GIDEP [22]. The decision that a component is counterfeit must be taken from data rather than from subject matter experts.


Conclusion
In this paper, we have presented all the counterfeit types currently corrupting the electronic component supply chain and the defects present in them. We have also presented a comprehensive taxonomy of the current counterfeit detec- tion methods. We have described various types of anti- counterfeit measures that prevent counterfeit ICs from entering into the supply chain. We believe that current efforts to address the counterfeiting problem are clearly not sufficient. More research is needed to implement effective test methods that are adaptable, as the counterfeiting pro- cess will become more sophisticated over time. Finally, new, low-cost, and robust anti-counterfeit mechanisms must be developed.