CSP assembly obstacles

The main driving force for chip-scale packaging is the market demand for miniaturization, especially for portable electronics. But no matter how big the drive is, new technologies always take time to get accepted because the infrastructure they support needs to be developed. The three biggest obstacles to the rapid acceptance of CSP are cost, PCB technology, and manufacturability. This article briefly describes an engineering project used to investigate manufacturability, including a collaborative group of representatives from companies involved in the infrastructure. A strong precedent for ball grid array (BGA) packaging has established a precedent in which the team designed and built a test carrier to explore the integration of CSP technology into manufacturing. Since cost and board technology are all related to the design of the real test carrier, a brief discussion is also made.

CSP technology trends

The function of the integrated circuit (IC) package is to provide spatial conversion of the bond pads on the chip to the vias or pads on the PCB. In the era of through-hole packaging, the pitch of the outer package pins is typically 100-mils (2.54 mm). Surface mount technology pushes the pitch of the surrounding leaded packages to 0.5 mm, now 0.4 mm. By reducing the pin pitch to 0.3mm to increase the packing density, severe resistance has been encountered. Using BGA technology to convert the surrounding pin package into an area arrangement, it provides a new alternative to suddenly relaxing the spacing.

Among the various packages developed over the past twenty to thirty years, a constant trend has emerged: packaging is increasingly difficult to achieve its spatial transformation function. We can make a comparison, using a double-row lead frame, a large number of outputs from the chip to the board; the other side is a plastic ball grid array (PBGA) package, high-density wiring on the substrate.

The emergence of CSP brings even greater difficulties. The front package provides the number of outputs from the die to the outer pins. However, for a CSP of the same size as the chip die, there is no chance of an output within the package; rather, an input from the bond pad to the external connection is necessary. Even for a CSP that is slightly larger than the chip size, the available space at the output is very limited. Therefore, most CSPs are constructed by non-traditional methods, such as flexible circuits, because the leadframe and printed circuit board are not capable of achieving the required high wiring density. Although the wiring problem inside the package can be solved by the construction method, the wiring problem outside the package still exists.

CSP barrier

PCB technology

Figure 1. PCB layout with CSP of 0.65mm pitch with 45 solder balls The basic problem with CSP is that silicon technology advances faster than PCB technology. All external pins have to be confined within the outline of the chip die or exposed. With the successive generation of silicon processing technology, the chip mode is reduced, and the external pins are inevitably reduced to beyond the conventional FR-4 wiring capability.

Figure 1 shows the board layout of a CSP with 45 solder balls aligned at 0.65mm pitch, showing that it can be routed on one layer using reasonable standard FR-4 design rules. However, if the pitch of the CSP is reduced from 0.65 mm to 0.5 mm, then more aggressive design rules are required. Packaging for higher pin counts at the same 0.65mm pitch is also expensive because it is necessary to use more than one wiring layer, possibly using blind vias. Therefore, today's demand for CSP is mostly limited to low leads. The number of feet, such as memory, is in the range of 0.65mm to 0.80mm. The CSP of the surrounding pins can reach a pitch of 0.5mm, but these are inherently limited to low pin counts.

Of course, the CSP cabling problem is not the only problem with the relatively rough design rules of the traditional FR-4. Miniaturization requires thinner lines and spaces and smaller vias, simply reducing board "real estate." As a result, the PCB industry is investing heavily in advanced board technology with combined layers and microvias, especially in Japan. As products with advanced board technology become more prevalent, they will put more complex CSPs into use. However, FR-4 still maintains the current standard due to its low cost.

Cost

Figure 2. CSP production forecast. Figure 2 shows a preview of CSP production worldwide. Today's yield - about 0.05% of the total IC - is very low. Another obstacle to accepting CSPs is cost. The current cost of CSP is very high and is typically 1.5 to 2 times more expensive than comparable traditional packaging. As production increases, costs will likely approach similar levels of traditional packaging. Most CSPs have an inherently low-cost structure that should eventually rival those based on leadframes, such as TSOP (thin small outline package). Figure 3 shows a forecast of future costs.

The factor that will affect the rate of cost reduction is how quickly the initial investment in research and development and equipment returns. The speed at which the output reaches the point where the scale effect is formed will also affect the cost.

Manufacturability

Figure 3. Cost prediction of CSP The third major obstacle is the assembly process of the board. An effective way to assess technology maturity and develop infrastructure is through a work partner that involves key roles in the “food chain”. In order to investigate the preparation status of CSP, a cooperative group was established: AMD provides silicon and packaging, Hadco and Zycon (two separate companies during the project) to provide boards, Solectron provides board design and assembly technology And Tessera offers packaging technology (μBGA?).

Until now, the traditional BGA has been accepted by the industry as "critical mass", which is accelerated by the ease of board assembly. The most dramatic aspect of its solder attachment is the self-centering of the solder balls during reflow. Because the micro BGA also has an array of solder balls, it also shares this advantageous property. On the other hand, the solder balls are smaller (compared to 0.3 mm and approximately 0.65 mm) and the pitch is finer (compared from 0.5 mm to 0.75 mm to 1.0 mm to 1.27 mm). The goal of the collaborative group is to establish the end result of these characteristics.

Board assembly evaluation and test carrier design

Today's applications for CSPs may be low pin count components such as memory and medium pin count components such as microprocessors (up to about 200). Therefore, one of the objectives of the collaborative group's project was to evaluate the manufacturability of these packages, in particular a 44-pin miniature BGA designed for flash memory and a test package of 188 inputs and outputs. The two spacings used for the memory are 0.65mm and 0.75mm, both of which are evaluated. The test package for the 188-I/O is 0.5 mm pitch.

Most CSP applications may include a variety of other packaging. In order to address the issues of manufacturing yield and design for manufacturing (DFM), a test carrier should include a mix of various components and should be double sided. Table 1 lists the optional components.

Table 1. Components selected for testing the carrier
Packing Pin count, spacing Number of boards per board
μBGA test package 44, 0.75mm 2
μBGA flash memory 44, 0.65mm 2
μBGA test package 188, 0.5mm 1
TQFP 100, 0.5mm 2
Plastic BGA 208, 1.27mm 1
The second type TSOP 24, 0.8mm 2
SOIC 16, 50 mil 2
SOIC 8, 50 mil 4
Chip capacitors ? 34
PCM CIA Edge Connector 68, 1.27mm 1
The board is a traditional FR-4 that is consistent with most portable products today. The basic reason for including the 0.5mm pitch, 188-pin micro BGA package - although difficult to route with conventional FR-4 - is to evaluate whether the board assembly process can be extended to the package as such, indicating future development Already ready. All components are internally bonded in a chain-chain configuration to match the cascade chain layout on the board. Therefore, it is possible to check the electrical continuity of each solder joint. The panels are manufactured using two surface treatments: an organic solder protectant (OSP) and a nickel/gold coating; HASL is not suitable for these fine pitch components.

Assembly process

Solder paste silk screen process

As with any fine-pitch assembly, the biggest concern is the silkscreen process of solder paste. A test was designed to test the effects of different stencil openings, template surface finishes, and solder paste types. Two solder pastes were studied, both of which are disposable and used in production for other closely spaced components. The printed solder paste is visually inspected for print quality and X-ray spectral analysis is used to measure the amount of solder paste. The result shows that the only variable that has a significant impact is the template opening. With the best openings, both solder paste types give the same good print quality.

Each of the 100 boards of each version is equipped with a 44-I/O micro BGA (0.75 mm and 0.65 mm pitch).

Evaluation of solder joint quality

The quality of the solder joints is evaluated by visual inspection, X-ray and metallographic cross sections. In addition, since all components are in a cascade chain, electrical continuity can be 100%. Two tin bridge defects were found, which were caused by misoperation. In other words, all chip sizes and soldering points of traditional packaging are of good quality, with good wetting and rounding. The total number of solder points, two defects is 12 parts per million (ppm, parts per milliom).

Solder joint reliability assessment

Figure 4. CSP reliability test The final stage of the project is the evaluation of the long-term reliability of the solder joint. The test carrier at this stage is similar to the manufacturability test vector except that another version of the CSP is included. This version will be a fine pitch BGA (FBGA) and is also designed for flash memory, but unlike the mini BGA package, because the solder ball pitch is 0.8mm and the FBGA lacks a compliant layer.

Since there are FBGA packages on the same board as the other components, then between the three flash packages - micro BGA, FBGA and TSOP - and the 188-pin micro BGA and the 100-pin TQFP (tape quad flat pack) There is an interesting comparison between them. The complete matrix of the experiment is shown in Figure 4.

Preconditioning is designed to simulate the temperature cycling and vibration that will occur during product transport. The stress test is quite standard; it is worth mentioning that the surface insulation resistance (SIR) is the focus on the accumulation of dirt due to the relatively small ground clearance of the CSP - and the mechanical deflection system ( MDS, mechanical deflection system), if it shows good correlation, it is a quick alternative to temperature cycling. Presumably, most of the interest will be concentrated on the ATC, which will provide a quantitative measure of weld fatigue defect sensitivity. Micro BGAs have a compliant layer that may produce the best results.

in conclusion

A manufacturing process has proven to be used in miniature BGA packages that are compatible with existing surface mount processes and can handle traditional surface mount packages on the same board. As with any fine pitch technology, the user should pay special attention to optimizing the quality of solder paste printing, which can be done with existing materials and traditional templates. With this problem, it is simple to obtain good results, and a yield of 12 ppm is obtained. The quality of the solder joints was confirmed by various tests. All three CSP pitches: 0.5 mm, 0.65 mm and 0.75 mm gave good results.

The quality of the solder joints is good, and the reliability results should be good, although the different package types behave differently. Reliability test results should be translated into results obtained in the final use environment of the product. Different packaging will suit different requirements. The inclusion of CSP in product design has not been confirmed due to the reliability test results.

Another practical barrier to limiting CSP technology to high pin counts and less than 0.65 mm pitch is the ability of board technology. The conventional FR-4 is sufficient for low pin count components with pitches as small as 0.65 mm. However, in addition to this, some higher density board technology is required, using laminate and micro via holes. Given that portable electronics manufacturers continue to push for miniaturization and increased functionality, this board technology is required even without CSP. As a result, major manufacturers are looking to introduce a variety of products that use high-density boards to provide the right platform to accept tighter-pitch CSPs.

Traditional BGAs have been rapidly accepted in the market because they achieve good manufacturing suitability in board assembly. This topic has achieved similar success with CSP, so we get an expectation: maybe CSP can be used more quickly than BGA.